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1 of 20 072401 features 8 or 32 kbytes of user nv ram integrated nv sram, real time clock, crystal, power-fail control circuit and lithium energy source totally nonvolatile with over 10 years of operation in the absence of power watchdog timer restarts an out-of-control processor alarm function schedules real-time related activities such as system wakeup programmable interrupt s and square wave output all registers are individually addressable via the address and data bus interrupt signals are active in power-down mode pin assignment ds1386/ds1386p ramified watchdog timekeepe r www.maxim-ic.com 1 intb ( intb ) 2 3 nc nc pfo v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 sqw nc 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 nc a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 inta x1 gnd v bat x2 ds1386 8k x 8 34-pin powercap module board (uses DS9034PCX powercap) 1 intb ( intb ) 2 3 nc nc pfo v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 sqw a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 inta x1 gnd v bat x2 ds1386 32k x 8 34-pin powercap module board (uses DS9034PCX powercap) int a inta 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 ds1386 32k x 8 32-pin encapsulated package v cc 32 30 29 28 27 26 25 24 23 22 21 19 20 15 16 18 17 v cc sqw we a 13 a 8 a 9 a 11 oe a 10 ce dq7 dq5 dq6 dq4 dq3 a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 intb a12 a6 dq2 gnd 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 ds1386 8k x 8 32-pin encapsulated package nc a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc sqw v cc we nc a 8 a 9 a 11 oe a 10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 intb a12 a6 dq2 gnd 15 16 18 17 dq4 dq3
ds1386/ds1386p 2 of 20 ordering information ds1386 xx-120 32-pin dip module 08 8k x 8 nv sram 32 32k x 8 nv sram *ds1386p xx-120 34-pin powercap ? module board 08 8k x 8 nv sram 32 32k x 8 nv sram *DS9034PCX powercap required (must be ordered separately) pin description inta - interrupt output a (open drain) intb (intb) - interrupt output b (open drain) a0-a14 - address inputs dq0-dq7 - data input/output ce - chip enable oe - output enable we - write enable v cc - +5v gnd - ground sqw - square wave output nc - no connection x1, x2 - crystal connection v bat - battery connection description the ds1386 is a nonvolatile static ram with a full-f unction real time clock (rtc), alarm, watchdog timer, and interval timer which are all accessible in a byte-wide fo rmat. the ds1386 contains a lithium energy source and a quartz crystal, which eliminates the need for any external circuitry. data contained within 8k or 32k by 8-bit memory and the timekeepin g registers can be read or written in the same manner as bytewide static ram. the timekeeping registers are located in the first 14 bytes of memory space. data is maintained in the ramified timekeeper by intelligent control circuitry, which detects the status of v cc and write protects memory when v cc is out of tolerance. the lithium energy source can maintain data and real time for over ten years in the absence of v cc . timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, da te, month, and year. the date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap year. the ramified timekeeper operates in either 24-hour or 12-hour format with an am/pm indicator. the watchdog timer provides alarm inte rrupts and interval timing between 0.01seconds and 99.99 seconds. the real time alarm provides for preset times of up to one week. interrupts for both watchdog and rtc will operate when system is powered down. either can provide system ?wake-up? signals.
ds1386/1386p 3 of 20 packages the ds1386 is available in two packages (32-pin di p module and 34-pin powercap module). the 32-pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (DS9034PCX) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1386p after the completion of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and ba ttery due to high temperatures required for solder reflow. the powercap is keyed to prevent revers e insertion. the powercap module board and powercap are ordered separately and shippe d in separate containers. the part number for the powercap is DS9034PCX. operation - read registers the ds1386 executes a read cycle whenever we (write enable) is inactive (high), ce (chip enable) and oe (output enable) are active (low). the unique ad dress specified by the address inputs (a0-a14) defines which of the registers is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address-i nput signal is stable, providing that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the latter occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. operation - write registers the ds1386 is in the write mode whenever the we (write enable) and ce (chip enable) signals are in the active (low) state after the address inputs ar e stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery state (t wr ) before another cycle can be initiated. data must be valid on the data bus with sufficient data set-up (t ds ) and data hold time (t dh ) with respect to the earlier rising edge of ce or we . the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output bus has been enabled ( ce and oe active), then we will disable the outputs in t odw from its falling edge. data retention the ramified timekeeper provides full functional capability when v cc is greater than 4.5 volts and write-protects the register contents at 4.25 volts ty pical. data is maintained in the absence of v cc without any additional support circuitry. the ds1386 constantly monitors v cc . should the supply voltage decay, the ramified timekeeper will automatically write-pro tect itself and all inputs to the registers become ?don?t care.? the two interrupts inta and intb (intb) and the internal clock and timers continue to run regardless of the level of v cc . however, it is important to insure that the pull-up resistors used with the interrupt pins are never pulled up to a value that is greater than v cc + 0.3v. as v cc falls below approximately 3.0 volts, a power switchi ng circuit turns the internal lith ium energy source on to maintain the clock and timer data and functionality. it is also required to insure that during this time (battery backup mode), the voltage present at inta and intb (intb) never exceeds 3.0v. during power-up, when v cc rises above approximately 3.0 volts, the pow er switching circuit connects external v cc and disconnects the internal lithium energy source. normal operation can resume after v cc exceeds 4.5 volts for a period of 200 ms.
ds1386/1386p 4 of 20 ramified timekeeper registers the ramified timekeeper has 14 registers, which are 8 bits wide that contain all of the timekeeping, alarm, and watchdog and control information. the cl ock, calendar, alarm, and watchdog registers are memory locations, which contain external (user-accessible) copies of the timekeeping data. the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see figure 1). the command register bits are affected by both internal and external functions. this register will be discussed later. the 8 or 32 kbytes of ram and the 14 external timekeeping registers are accessed from the external address and data bus. registers 0, 1, 2, 4, 6, 8, 9, and a contain time of day and date information (see figure 2). time of day information is stored in bcd. registers 3, 5, and 7 contain the t ime of day alarm information. time of day alarm information is stored in bcd. register b is the command register and information in this register is binary. registers c and d are the watchdog alarm regi sters and information, which is stored in these two registers, is in bcd. registers e through 1fff or 7fff are user bytes and can be used to maintain data at the user?s discretion. clock accuracy (dip module) the ds1386 is guaranteed to keep time accura cy to within 1 minute per month at 25c. clock accuracy (powercap module) the ds1386p and DS9034PCX are each individually tested for accuracy . once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25 c.
ds1386/1386p 5 of 20 block diagram figure 1
ds1386/1386p 6 of 20 time of day registers registers 0, 1, 2, 4, 6, 8, 9, and a contain time of day data in bcd. ten bits within these eight registers are not used and will always read 0 regardless of how they are written. bits 6 and 7 in the months register (9) are binary bits. when set to logic 0, eosc (bit 7) enables the real time clock oscillator. this bit is set to logic 1 as shipped from dallas semiconductor to prevent lithium energy consumption during storage and shipment (dip module only). this bit will normally be turned on by the user during device initialization. however, the osc illator can be turned on and off as necessary by setting this bit to the appropriate level. bit 6 of this same byte cont rols the square wave output. when set to logic 0, the square wave output pin will output a 1024 hz square wa ve signal. when set to logic 1 the square wave output pin is in a high impedance state. bit 6 of the hours register is defined as the 12- or 24-hour select bit. when set to logic 1, the 12-hour format is se lected. in the 12-hour format, bit 5 is the am/pm bit with logic 1 being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). the time of day registers are updated every 0.01 seconds from the real time clock, except when the te bit (bit 7 of register b) is set low or the cl ock oscillator is not running. the pr eferred method of synchronizing data access to and from the ramified timekeeper is to access the command register by doing a write cycle to address location 0b and setting the te bit (transfer enable bit) to a logic 0. this will freeze the external time of day registers at the present reco rded time, allowing access to occur without danger of simultaneous update. when the watch re gisters have been read or written, a second write cycle to location 0b, setting the te bit to a logic 1, will put the time of day registers back to being updated every .01 second. no time is lost in the real time clock becau se the internal copy of the time of day register buffers is continually incremented while the external memory registers are frozen. an alternate method of reading and writing the time of day registers is to ignore synchronization. however, any single read may give erroneous data as the r eal time clock may be in the proc ess of updating the external memory registers as data is being read. the internal copi es of seconds through years are incremented, and the time of day alarm is checked during the period that hundreds of seconds reads 99 and are transferred to the external register when hundredths of seconds roll fr om 99 to 00. a way of making sure data is valid is to do multiple reads and compare. writing the regist ers can also produce erroneous results for the same reasons. a way of making sure that the write cycle ha s caused proper update is to do read verifies and re- execute the write cycle if data is not correct. while the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structur e of the ramified timekeeper. time of day alarm registers registers 3, 5, and 7 contain the time of day alarm registers. bits 3, 4, 5, and 6 of register 7 will always read 0 regardless of how they are written. bit 7 of registers 3, 5, and 7 are mask bits (figure 3). when all of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. an alarm will be generated every day when bit 7 of register 7 is set to a logic 1. similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1. when bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1 (seconds) rolls from 59 to 00. time of day alarm registers are written and read in the same format as the time of day registers. the time of day alarm flag and interrupt are always cleared when alarm registers are read or written.
ds1386/1386p 7 of 20 watchdog alarm registers registers c and d contain the time for the watchdog alarm. the two registers contain a time count from 00.01 to 99.99 seconds in bcd. the value written into the watchdog alarm registers can be written or read in any order. any access to register c or d will cause the watchdog alarm to reinitialize and clears the watchdog flag bit and the watchdog interrupt out put. when a new value is entered or the watchdog registers are read, the watchdog timer will start counting down from the entered value to zero. when zero is reached, the watchdog interrupt output will go to the active state. the watchdog timer countdown is interrupted and reinitialized back to the entered va lue every time either of the registers are accessed. in this manner, controlled periodic accesses to the watchdog timer can prevent the watchdog alarm from going to an active level. if access does not occu r, countdown alarm will be repetitive. the watchdog alarm registers always read the entered value. th e actual countdown register is internal and is not readable. writing registers c and d to 0 will disable the watchdog alarm feature.
ds1386/1386p 8 of 20 ds1386 ramifed watchdog timekeeper registers figure 2
ds1386/1386p 9 of 20 time of day alarm mask bits figure 3 register (3) minutes (5) hours (7) days 1 1 1 alarm once per minute 0 1 1 alarm when minutes match 0 0 1 alarm when hours and minutes match 0 0 0 alarm when hours, minutes and days match note: any other bit combinations of mask bit settings produce illogical operation. command register address location 0bh is the command register where ma sk bits, control bits and flag bits reside. the operation of each bit is as follows: te - bit 7 transfer enable-this bit when set to a logic 0 will disable the transfer of data between internal and external clock registers. the contents in the external clock registers are now frozen and reads or writes will not be affected with updates. this bit must be se t to a logic 1 to allow updates. ipsw - bit 6 interrupt switch-when set to a logic 1, inta is the time of day alarm and intb/( intb ) is the watchdog alarm. when set to logic 0, this bit reverses the output pins. inta is now the watchdog alarm output and intb/( intb ) is the time of day alarm output. ibh/lo - bit 5 interrupt b sink or source current-when this bit is set to a logic 1 and v cc is applied, intb/( intb ) will source current (see dc characteristics ioh). when this bit is set to a logic 0, intb will sink current (see dc characteristics iol). pu/lvl - bit 4 interrupt pulse mode or level mode - this bit determines whether both interrupts will output a pulse or level signal. when set to a logic 0, inta and intb/( intb ) will be in the level mode. when this bit is set to a logic 1, the pulse mode is selected and inta will sink current for a minimum of 3 ms and then release. intb/( intb ) will either sink or source cu rrent, depending on the condition of bit 5, for a minimum of 3 ms and then release. intb will only source current when there is a voltage present on v cc . wam - bit 3 watchdog alarm mask - when this bit is set to a logic 0, the watchdog interrupt output will be activated. the activated state is deter mined by bits 1,4,5, and 6 of the command register. when this bit is set to a logic 1, the watchdog interrupt output is deactivated. tdm - bit 2 time of day alarm mask - when this bit is set to a logic 0, the time of day alarm interrupt output will be activated. the activated state is determined by bits 0,4,5, and 6 of the command register. when this bit is set to a logic 1, the time of day alarm interrupt output is deactivated.
ds1386/1386p 10 of 20 waf - bit 1 watchdog alarm flag - this bit is set to a logic 1 when a watchdog alarm interrupt occurs. this bit is read only. the bit is reset when any of the watchdog alarm registers are accessed. when the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only during the time the interrupt is active. tdf - bit 0 time of day flag - this is a read only bit. this bit is set to a logic 1 when a time of day alarm has occurred. the time the alarm occurred can be determined by reading the time of day alarm registers. this bit is reset to a logic 0 state when any of the time of day alarm registers are accessed. when the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only during the time the interrupt is active.
ds1386/1386p 11 of 20 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +7.0v operating temperature 0c to 70c storage temperature -40c to +70c soldering temperature see j-std- 020a specification (see note 14) * this is a stress rating only and f unctional operation of the device at th ese or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 10 input logic 1 v ih 2.2 v cc +0.3 v 10 input logic 0 v il -0.3 +0.8 v 10 dc electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a output leakage current i lo -1.0 +1.0 a i/o leakage current i lio -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.1 ma 13 standby current ce =2.2v i ccs1 3.0 7.0 ma standby current ce =v cc -0.5 i ccs2 2.0 4.0 ma active current i cc 85 ma write protection voltage v tp 4.0 4.25 4.5 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 715pf output capacitance c out 715 pf input/output capacitance c i/o 715pf
ds1386/1386p 12 of 20 ac electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) ds1386xx-120 parameter symbol min max units notes read cycle time t rc 120 ns 1 address access time t acc 120 ns ce access time t co 120 ns oe access time t oe 100 ns oe or ce to output active t coe 10 ns output high z from deselect t od 40 ns output hold from address change t oh 10 ns write cycle time t wc 120 ns write pulse width t wp 110 ns 3 address setup time t aw 0ns write recovery time t wr 10 ns output high z from we t odw 40 ns output active from we t oew 10 ns data setup time t ds 85 ns 4 data hold time t dh 10 ns 4,5 inta , intb pulse width t ipw 3 ms 11,12
ds1386/1386p 13 of 20 read cycle (note 1) write cycle 1 (notes 2, 6, 7) write cycle 2 (notes 2, 8)
ds1386/1386p 14 of 20 timing diagram: interrupt outputs pulse mode (see notes 11 and 12) power-down/power-up timing
ds1386/1386p 15 of 20 ac electrical characteristic s power-up/power-down timing (0 c to 70 c) parameter symbol min max units notes ce high to power fail t pf 0ns recovery at power up t rec 200 ms v cc slew rate power down t f 4.0 v cc 4.5v 300 s v cc slew rate power down t fb 3.0 v cc 4.25v 10 s v cc slew rate power up t r 4.5v v cc 4.0v 0s expected data retention t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
ds1386/1386p 16 of 20 notes 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of the ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds or t dh are measured from the earlier of ce or we going high. 5. t dh is measured from we going high. if ce is used to terminate the write cycle, then t dh = 20 ns for -120 parts and t dh = 25 ns for -150 parts. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each ds1386 is marked with a four-digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined for dip modules as starting at the date of manufacture. 10. all voltages are referenced to ground. 11. applies to both interrupt pins when the alarms are set to pulse. 12. interrupt output occurs within 100 ns on the alarm condition existing. 13. both inta and intb ( intb ) are open drain outputs. 14. real-time clock modules (dip) can be successfully processed thro ugh conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap version: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or a pply the soldering iron to leads for more than 3 (three) seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
ds1386/1386p 17 of 20 ac test conditions: ac test conditions input levels: 0v to 3v output load 50 pf + 1ttl gate transition times: 5 ns input pulse levels: 0-3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns ds1386 32-pin 740-mil module pkg 32-pin dim min max a in mm 1.680 42.67 1.740 44.20 b in mm 0.715 18.16 0.740 18.80 c in mm 0.335 8.51 0.365 9.27 d in mm 0.075 1.91 0.105 2.67 e in mm 0.015 0.38 0.030 0.76 f in mm 0.140 3.56 0.180 4.57 g in mm 0.090 2.29 0.110 2.79 h in mm 0.590 14.99 0.630 16.00 j in mm 0.010 0.25 0.018 0.46 k in mm 0.015 0.38 0.025 0.64
ds1386/1386p 18 of 20 ds1386p pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: for the powercap version: a. dallas semiconductor recommends that powercap module base s experience one pass though solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or a pply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
ds1386/1386p 19 of 20 ds1386p with DS9034PCX attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030
ds1386/1386p 20 of 20 recommended powercap module land pattern pkg inches dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 -

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